The present invention relates to a semiconductor memory device, and more precisely to a setup/hold time control circuit which controls a setup/hold time of signals input through multiple ports.
In a semiconductor memory device input signals such as addresses, commands, and data are input from an outside source through ports.
Control of a setup time and a hold time for each of the input signals is necessary to improve the performance of the semiconductor memory device.
Margin and timing are important factors when controlling the setup time and the hold time of the input signals.
The semiconductor memory device is typically configured with a buffer to sufficiently secure the margin of the setup time and the hold time of the input signals for each port. The buffer is used to obtain the margin of the setup time and the hold time required by product specifications.
Further, the semiconductor memory device must have the timing between the input signals controlled in order to improve the setup/hold performance.
In a high-speed operating graphic memory, the input signals that are input through multiple ports are controlled simultaneously. As such, if the setup/hold timings of the input signals between each port are not the same, it is difficult to perform the high-speed operation. For example, in a case where a data bus of 32 bits is controlled in a unit of 8 bits, the input signals that are input to the 8 ports must have same setup/hold timing.
As the semiconductor memory device increases to a high speed, the input signals are required to have lower setup/hold time. However, as the production process of semiconductor memory devices is advanced, the critical dimension becomes fine and a fine difference in the gates influences the setup/hold time of each port. Consequently, it becomes difficult to control the setup/hold timings of the input signals such that they are the same for the multiple ports.